MT-074 tutorial differential drivers for precision adcs differential input adc characteristics many high performance adcs are now being de signed with differential inputs. a fully differential adc design offers the advantages of good common-mode re jection, reduction in second-order distortion products, an d simplified dc trim algorithms. although they can be driven single-ended, a fully differential driver usually optimizes overall performance. one of the most common ways to drive a differen tial input adc is with a transformer. however, there are many applications wher e the adcs cannot be driven w ith transformers because the frequency response must extend to dc. in these cases, differential drivers are required. this tutorial focuses on driving high resolution 16- to 18-bit adcs with sampling rates up to 10 msps. the bandwidth of the input signals is generally limited to a few mhz. tutorial mt-075 discusses differential amplifiers suit able for driving higher speed adcs. most high performance cmos switched capacito r pipelined adcs have differential inputs. similar to that shown in figure 1. rev.0, 10/08, wk page 1 of 5 figure 1: simplified input circuit for a typical unbuffered switched capacitor cmos sample-and-hold the differential structure is ty pically carried through most of the adc. this makes matching requirements easier as well as reduces second-o rder products. in addition, the differential structure helps in common-mode noise rejection. v inb + - z in is a function of: ? ? track mode vs. hold mode input frequency a v ina c p c p s1 s2 s3 s4 s6 s5 c h 5pf c h 5pf switches shown in track mode s7 z in
MT-074 note that the sha switches are connected directly to each of the inputs. switching transients can be significant, because there is no isolation buffer. the driv e amplifier settling time to the transients must be fast enough so that the amplifier settles to the required accuracy in less than one-half the sampling period (this se ttling time must include the effects of any external series resistance). the differential input impedance of this stru cture is dynamic and changes when the sha switches between the sample mode and the hold mode. in addition, the impedance is a function of the analog input frequency. in the track mode (shown in the figure), the input signal charges an d discharges the hold capacitors, c h . when the circuit switches to the hold mo de the switches reverse their positions, and the voltage across the hold capacito rs is transferred to the outputs. it is highly recommended that this type of input be driven differentially for common-mode rejection of the switching transients. while it is possible to drive them single-ended (with one input connected to the appropriate common-mode voltage), degradation in sfdr will occur because the even-order distortion products are no longer rejected. figure 2 (a) shows each of the differential inputs of a typical unbuffered cmos adc as well as the sampling clock. the inputs were driven with a 50 source resistance. note that a transient occurs on each edge of the sampling clock because of the switching action previously described. figure 2(b) shows the differential input signal to the adc under the same conditions as (a). note that most of the transient current glitch es are cancelled because they are common-mode signals. note that for cancellation to be optimum the two inputs must be driven from a balanced source impedance (the real and reactive com ponents of the impedance must be matched). ? differential charge transient is symmetrical around mid-scale and dominated by linear component ? common-mode transients cancel with equal source impedance note: data taken with 50 source resistances (a) single ended (b) differential sampling clock sampling clock ? differential charge transient is symmetrical around mid-scale and dominated by linear component ? common-mode transients cancel with equal source impedance note: data taken with 50 source resistances (a) single ended (b) differential sampling clock sampling clock figure 2: typical single-ended (a) and differential (b) input transients of cm os switched capacitor adc page 2 of 5
MT-074 driving precision 16- and 18-bi t differential input adcs figure 3 shows the ada4941-1 driving the 18-bit pulsar family of adcs which have switched capacitor inputs. this is a common application wh ere the signal is single-ended and bipolar and the adc input is differential. because of the hi gh resolution, the drive am plifier must have low distortion, low noise, and high dc accuracy, as we ll as the capability of performing the single- ended to differential conversion. the ada4941-1 is a low power (2.2 ma @ 3.3 v), low noise (10.2 nv/ hz @ 1 khz), low distortion (110 dbc @ 100 khz) differential driver for adcs up to 18 bits. small signal bandwidth is 31 mhz. the amplifier has rail-to-rail output, high input impedance, and a user-adjustable gain. the ada4941-1 consists of two op amps. the lo wer one in the figure is configured as a non- commited non-inverting buffer (with external feedback resistor ) and drives an inverting amplifier. the feedforward and feedback resistor s for the inverting amplifier are included in the ic. although there is extra phase shift and delay through the inverting amplifier, this does not introduce significant error at the frequencie s of interest (up to 1 mhz or 2 mhz). +5v +2.1v +1.75v 9.53k 10.0k 8.45k 0.1f 0.1f 11.3k 4.02k 806 adr444 +5v v ref = +4.096v 0.1f ref +5v vdd in+ in? + + ? ? c f v in = 10v +2.1v +/? 2v +2.1v ? /+ 2v ada4941-1 41.2 41.2 3.9nf 3.9nf ad7690, 400ksps ad7691, 250ksps 18-bit pulsar adcs lpf cutoff = 1mhz v cm = +2.1v r r 0.1f v ref = +4.096v input range= 8.192v p-p diff. 10.2nv/ hz after filter, noise = 13v rms due to amp signal = 8v p-p differential snr = 107db @ adc input snr = 100db for ad7690 ? ? ? figure 3: ada4941-1 driving ad7690 18-bit pulsar? adc in +5v application in this application, the two resistor dividers set the output common-mode voltage of the ada4941-1 to +2.1 v so that the out put only has to go to within 100 mv of ground. this allows sufficient headroom for the rail-to-rail output stages of the amplifier and allows the entire circuit to operate on a single +5 v supply. page 3 of 5
MT-074 the input range of the ad7690 and ad7691 is 2 ?v ref p-p differential. the reference used is the adr444 which is a 4.096 v reference. the 41.2 resistors and the 3.9 nf capacitors for a lowpass filter with a cutoff frequency of 1 mhz, suitable for use with the ad7690 which has an input bandwidth of 9 mhz. the ada4941-1 has an output noise spectra l density of 10.2 nv/ hz for the configuration selected. integrated over the filter bandwid th, this is 13 v rms. this corresponds to an snr due to th e op amp of 107 db, which is 7 db better than the 100 db snr of the adc. figure 4 shows another example of driving a high performance i cmos? pulsar? adc (e.g., ad7634 ). there are many industrial applications wher e signals as great as 10 v are standard. the icmos family of adcs was developed to ha ndle these applications. most icmos pulsar adcs have differential inputs. here, the ada4922-1 is driving a 16-bit or 18-bit i cmos pulsar adc. it performs a single- ended to differential conversion. +12v +5v vdd in+ in? + + ? ? + / ? 10v ?/ + 10v ada4922-1 41.2 41.2 3.9nf 3.9nf 18, 16-bit icmos pulsar adcs (e.g., ad7634) lpf cutoff = 1mhz output v n = 12nv/ hz r r ?12v v in = 10v 0.1f 0.1f vcc vee 0.1f 0.1f 0.1f ad7634 snr = 100db after filter, noise = 15v rms due to amp signal = 40v p-p differential snr = 119db @ adc input ? ? ? figure 4: ada4922-1 driving ad7634 18-bit icmos pulsar adc in 12v industrial application the ada4922-1 is a differential driver for 16-b it to 18-bit adcs that have differential input ranges up to 40 v p-p. small signal bandwidth is 38 mhz. the ada4922-1 is manufactured on adi?s proprietary second-genera tion xfcb process that enable s the amplifier to achieve excellent noise and distortion perf ormance on high supply voltages. noise calculations using the 1 mhz lowpass filt er yield 15 v rms for the op amp. the signal range of the adc is 40 v p-p, whic h is 14.14 v rms. this yields an snr of 119 db due to the op amp alone. page 4 of 5
page 5 of 5 MT-074 using the ad7634 snr of 100 db, the rms adc input noise contribution is ca lculated to be 141 v rms. the combined input adc noise is theref ore 142 v rms, and the contribution due to the op amp is almost negligible. references 1. hank zumbahlen, basic linear design , analog devices, 2006, isbn: 0-915550-28-1. also available as linear circuit design handbook , elsevier-newnes, 2008, isbn-10: 0750687037, isbn-13: 978- 0750687034. chapter 2. 2. walter g. jung, op amp applications , analog devices, 2002, isbn 0-916550-26-5, also available as op amp applications handbook , elsevier/newnes, 2005, isbn 0-7506-7844-5. chapter 3. 3. walt kester, analog-digital conversion , analog devices, 2004, isbn 0-916550-27-3, chapter 6. also available as the data conversion handbook , elsevier/newnes, 2005, isbn 0-7506-7841-0, chapter 6. 4. walt kester, high speed system applications , analog devices, 2006, isbn-10: 1-56619-909-3, isbn-13: 978-1-56619-909-4, chapter 2. copyright 2009, analog devices, inc. all rights reserved. analog devices assumes no responsibility for customer product design or the use or application of customers? products or for any infringements of patents or rights of others which may result from analog devices assistance. all trad emarks and logos are property of their respective holders. information furnished by analog devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog devices regarding technical accuracy and topicality of the content provided in analog devices tutorials.
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